`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    00:33:00 11/05/2008 
// Design Name: 
// Module Name:    ControllerReg 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ControllerReg(
	input clock,
	input reset,
	input [5:0] controller,
	output controllerSelect,
	output reg [15:0] controllerOut,
	output power
    );

always@(posedge clock)
begin
	if(reset)
		controllerOut <= 16'd0;
	else	
		begin
		controllerOut[15:4] <= 12'd0;
		if(controller == 6'b111111)
		begin
		controllerOut[3:0] <= 4'h0;
		end
		else if(controller == 6'b011111)
		controllerOut[3:0] <= 4'h1;
		else if(controller == 6'b101111)
		controllerOut[3:0] <= 4'h2;
		else if(controller == 6'b110111)
		controllerOut[3:0] <= 4'h3;
		else if(controller == 6'b111011)
		controllerOut[3:0] <= 4'h4;
		else if(controller == 6'b111101)
		controllerOut[3:0] <= 4'h5;
		else if(controller == 6'b111110)
		controllerOut[3:0] <= 4'h6;
		else
		begin
			controllerOut[3:0] <= 4'h0;	
		end
		end
end
assign power = 1;
assign controllerSelect = 1;
endmodule
